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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:10:21 02/25/2011 
-- Design Name: 
-- Module Name:    interfaz - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.Definitions.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity interfaz is
    Port ( PC : in STD_LOGIC_VECTOR (9 downto 0);
			  clk_i : in  STD_LOGIC;
			  proc_state : in processor_state;
           instr_cyc_o : out  STD_LOGIC;
           instr_stb_o : out  STD_LOGIC;
           instr_ack_i : in  STD_LOGIC;
           instr_addr_o : out  instr_addr_type;
           instr_word_i : in  instr_word_type;
           data_cyc_o : out  STD_LOGIC;
           data_stb_o : out  STD_LOGIC;
           data_we_o : out  STD_LOGIC;
           data_ack_i : in  STD_LOGIC;
           data_addr_o : out  data_addr_type;
           data_word_o : out  data_word_type;
           data_word_i : in  data_word_type;
           port_cyc_o : out  STD_LOGIC;
           por_stb_o : out  STD_LOGIC;
           port_we_o : out  STD_LOGIC;
           port_ack_i : in  STD_LOGIC;
           port_addr_o : out  port_addr_type;
           port_word_o : out  port_word_type;
           port_word_i : in  port_word_type;
			  ir : out instr_word_type;
			  pc_out : in instr_addr_type;
           clr_i : in  STD_LOGIC);
end interfaz;

architecture Behavioral of interfaz is

begin
	process (clk_i,clr_i,proc_state,pc,enable_IR)
	begin
		if (proc_state=fetch) then
			instr_cyc_o <= '1';
			instr_stb_o <= '1';
			instr_addr_o <= pc;
			if (enable_IR = '1') then
				--ir <= instr_word_i; -- Obtener la instr_word_i de la ROM de instrucciones
				instr_cyc_o <= '0';
				instr_stb_o <= '0';
				instr_ack_i <= '1';
			end if;
		end if;
	end process;
end Behavioral;
